Refactor Risc-V cpu features#1291
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AntoinePrv wants to merge 1 commit intoxtensor-stack:masterfrom
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@serge-sans-paille this is the same refactor we did for arm. |
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LGTM with the minor nits I left on 989cdd4#r181925820 addressed. |
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sorry, the extra gcc failure should be fixed once I merge #1293, can you rebase on it afterward? |
JohanMabille
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Apr 10, 2026
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Major change was that the
getauxvalcheck for RVV was gated bydefined(__riscv_vector)(compile time availability), which is the same sort of bug we fixed in #1252 #1253.